1. Field of the Invention
The present invention relates to a process for fabricating semiconductor devices, and more particularly to a monolithic high-Q inductance device and a process for fabricating the same.
2. Description of the Prior Art
Many digital and analog circuits have been successfully mass-produced by using VLSI (very large scale integrated) technology. However, radio frequency (RF) circuits, such as those used in cellular telephones, wireless modems, and other types of communication equipment, have not yet been completely implemented with integrated circuits (ICs).
A lump-sum equivalent circuit of a conventional inductance device is shown in FIG. 1, in which L indicates the inductance, Rs the series resistance, and Cd the parasitic capacitance. Quality factor (hereinafter, Q value) refers to the quality of an inductance device. It is known that the inductance generated by an ideal conducting coil has an infinitely large Q value, and thus there is no energy loss. However, to date, it has not been possible to obtain an inductance device having an infinitely large Q value. Many attempts have been made to decrease the energy loss of the inductance in order to manufacture an inductance device having high Q-value.
A conventional inductance device, as shown in FIG. 2, has an inductor formed by a plurality of spiral conducting lines so as to decrease the serial resistance. The numerals in FIG. 2 indicate elements as follows: 10xcx9cthe substrate, 11xcx9cthe first dielectric layer, 12xcx9cthe conducting layer, 13xcx9cthe second dielectric layer, 15xcx9cthe via, 16xcx9cthe first spiral conducting line, 17xcx9cthe second dielectric layer, 20xcx9cthe first spiral via, 21xcx9cthe second spiral conducting line, 22xcx9cthe fourth dielectric layer, 25xcx9cthe second spiral via, 26xcx9cthe third spiral conducting line, and 27xcx9cthe passivation layer. However, by the spiral conducting lines, both the area of the inductor and the parasitic capacitance are increased.
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide an inductance device with high-Q and to provide a method for fabricating the same.
The above objects of the present invention can be achieved by providing a method for fabricating a high-Q inductance device. A first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. A passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed within the space around the spiral conducting line.
According to the method for fabricating the high-Q inductance device of the present invention, a spiral air gap is formed within the space around the spiral conducting line. Since air has a very low dielectric constant, the parasitic capacitance can be decreased. Therefore, the Q value of the inductance device of the present invention can be effectively increased.
To decrease the serial resistance further, the inductance device of the present invention can also include a plurality of spiral conducting lines rather than only one spiral conducting line. For example, an inductance device having three spiral conducting lines can be fabricated according to the following procedures. First, a first dielectric layer is formed on the semiconductor substrate. Then, a first spiral conducting line is formed above the first dielectric layer. Then, a third dielectric layer is formed above the first spiral conducting line and the first dielectric layer, such that a first spiral air gap is formed within the space around the first spiral conducting line. A first spiral via is formed within the third dielectric layer above the first spiral conducting line. Subsequently, a second spiral conducting line is formed on the first spiral via, and a fourth dielectric layer on the second spiral conducting line and the third dielectric layer, such that a second spiral air gap is formed within the space around the second spiral conducting line. A second spiral via is formed within the fourth dielectric layer above the second spiral conducting line, and a third spiral conducting line is formed on the second spiral via. Finally, a passivation layer is formed on the third spiral conducting line and the fourth dielectric layer, such that a third spiral air gap is formed within the space around the third spiral conducting line. By means of the at least one spiral conducting line, the resistance of the inductance device can be decreased.